Computer Architecture Exam MCQs – Practice Test 4 (Chapter 10)

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Instruction Level Parallelism MCQs – Practice Test 4 PDF Download

MCQ 16: Determining the whole branch penalty for the buffer of branch-target, assuming that the Hit rate and the Prediction accuracy is 90%:

0.32
0.38
1.38
0.28

MCQ 17: Multithreading allowing multiple-threads for sharing the functional units of a:

multiple processor
single processor
dual core
corei5

MCQ 18: The eliminating stage of WAR and WAW hazards is often called:

execution
anti-dependence
data hazards
dispatch

MCQ 19: The maximum performance measurement, attainable by the implementation is:

ideal pipeline CPI
ideal pipeline CDI
ideal pipeline CDA
initial pipeline CPI

MCQ 20: The goal of software techniques and hardware techniques is to exploit:

parallelism
scalability
supervision
compatibility

Instruction Level Parallelism Exam Prep – Computer Architecture Notes App & e-Book

Exploiting Memory MCQs

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Networks, Storage and Peripherals MCQs

Processor Datapath and Control MCQs

Computer Memory Review MCQs

Computer Architecture and Organization MCQs

Instruction Set Principles MCQs

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