Computer Architecture Certification MCQs – Practice Test 3 (Chapter 10)

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Instruction Level Parallelism Quiz – Practice Test 3 PDF Download

MCQ 11: Load and store instruction waits until the:

buffers are empty
stations are empty
buffers are full
stations are full

MCQ 12: The number of bits in a predictor: (m,n) is:

2m * 2 * number of prediction entries selected by the branch address
(2)² * n * number of prediction entries selected by the branch address
2m * number of prediction entries selected by the branch address
2m * n * number of prediction entries selected by the branch address

MCQ 13: Combination of instructions, such as compare the following branch and combining them into a one-operation, is taken by:

instruction decode
instruction fetch
macro-op fusion
micro-op fusion

MCQ 14: The primary challenge for every multiple-issue processors is trying to exploiting a large amount of:

MCQ 15: Which one of the following is used for out-of-order instruction execution in a Tomasulo algorithm?

ordered buffer
reorder buffer
data buffer
control buffer

Computer Architecture Quiz App & e-Book – Instruction Level Parallelism Certification Guide

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