Instruction Level Parallelism Learning App | Computer Architecture Quiz e-Book PDF

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Computer Architecture Certification MCQs – Practice Test 3 (Chapter 10)

Instruction Level Parallelism Quiz with Answers PDF Download – Test 3

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Instruction Level Parallelism Quiz – Practice Test 3 PDF Download

MCQ 11: Load and store instruction waits until the:

  1. buffers are empty
  2. stations are empty
  3. buffers are full
  4. stations are full

MCQ 12: The number of bits in a predictor: (m,n) is:

  1. 2m * 2 * number of prediction entries selected by the branch address
  2. (2)2 * n * number of prediction entries selected by the branch address
  3. 2m * number of prediction entries selected by the branch address
  4. 2m * n * number of prediction entries selected by the branch address

MCQ 13: Combination of instructions, such as compare the following branch and combining them into a one-operation, is taken by:

  1. instruction decode
  2. instruction fetch
  3. macro-op fusion
  4. micro-op fusion

MCQ 14: The primary challenge for every multiple-issue processors is trying to exploiting a large amount of:

  1. IP
  2. FLP
  3. FP
  4. ILP

MCQ 15: Which one of the following is used for out-of-order instruction execution in a Tomasulo algorithm?

  1. ordered buffer
  2. reorder buffer
  3. data buffer
  4. control buffer

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