Computer Architecture MCQs - Chapter 15
Pipelining in Computer Architecture Multiple Choice Questions (MCQs) PDF Download - 1
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The MCQ: By resolving structural hazard, working of the processor becomes; "Pipelining in Computer Architecture" App Download (Free) with answers: Slower; Faster; Stalled; Large; for free online classes. Solve Logical Operations Quiz Questions, download Google eBook (Free Sample) for best online schools for computer science.
Pipelining in Computer Architecture MCQ with Answers PDF Download: Quiz 1
By resolving structural hazard, working of the processor becomes
- faster
- slower
- stalled
- large
Pipelining increases the CPU instruction throughput but it reduces an
- resuming time
- terminating time
- execution time
- none of above
In the following instruction set DADD R1,R2,R3; DSUB R4,R1,R5; AND R6,R1,R7; OR R8,R1,R9; xOR R10,R1,R11, all the instructions after the DADD use the result of the
- dsub instruction
- dadd instruction
- and instruction
- or instruction
If any instruction in A1, . . ., A4, D, M1, . . ., M7 has the same register destination as this instruction, then the possible solution is
- stalling the issue of the instruction in id
- stalling the issue of the instruction in ex
- stalling the issue of the instruction in dec
- stalling the issue of the instruction in mem
The contention for the usage of a hardware device is called
- structural hazard
- control hazard
- deadlock
- data hazard
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Operating Systems Mock Tests
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Operating Systems MCQ with Answers
- Secondary memory of computer system is also called
- A properly designed operating system must ensure that an incorrect (or malicious) program cannot cause other programs to execute
- To run a program this Setup involves an amount of
- Program counter contains address of
- Kernel mode of operating system runs when mode bit is
Pipelining in Computer Architecture MCQ Book Questions
- A stall is commonly known as
- Effectiveness of any branch prediction scheme depends both on accuracy and frequency of conditional branches, which vary in SPEC from
- If an exception is raised and succeeding instructions are executed completely, then processor is said to have
- Situations that prevent next instruction in instruction stream, from executing during its designated clock cycle are known as
- Pipelining that allows achieving higher clock rates by decomposing five-stage integer pipeline into eight stages, is referred to as