Computer Architecture Cerification Guide: Practice Test 3 (Chapter 15)

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Pipelining in Computer Architecture Exam Questions and Answers PDF Download: Test 3

MCQ: 11

Every time during execution time if the event occurs at the same place with the same data and memory allocation is known as

asynchronous
synchronous
delayed
stalled

MCQ: 12

Pipeline overhead arises from the combination of pipeline register delay and

hit rate
clock cycle
cycle rate
clock skew

MCQ: 13

Each of the clock cycles from the previous section of execution becomes a

pipe stage
previous stage
stall
processor cycle

MCQ: 14

Which one of the following has been developed specifically for pipelined systems?

improving software
speed up utilities
optimizing compilers
all of above

MCQ: 15

The set of instructions examined as candidates for potential execution is called the

frame
register
window
blocked

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