Computer Architecture MCQs – Practice Test 2 (Chapter 15)

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Pipelining in Computer Architecture MCQ – Practice Test 2 PDF Download

MCQ 6: Splitting the cache into separate instruction and data caches or by using a set of buffers, usually called:

cache buffer
data buffer
instruction buffer
none of above

MCQ 7: The ideal CPI (Cycle per Instruction) on a pipelined processor is almost always:

MCQ 8: The fetch and execution cycles are interleaved with the help of:

clock
modification unit
fetch cycle
program counter

MCQ 9: A stall is commonly known as:

pipeline bubble
bubble
hazard
both a and b

MCQ 10: The pipelining process is also known as:

pipeline interlock
assembly line operation
stall interlock
stall deadlock

Computer Architecture Notes App & e-Book – Pipelining in Computer Architecture Exam Prep

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