Computer Architecture MCQs – Practice Test 1 (Chapter 21)

Thread Level Parallelism MCQs with Answers PDF Download – Test 1

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Thread Level Parallelism MCQs – Practice Test 1 PDF Download

MCQ 1: When performing a looping operation, the instruction gets stored in the:

memory
cache
registers
system heap

MCQ 2: A lock which causes a thread trying to acquire it to simply wait in a loop while repeatedly checking if the lock is available is known as:

spin locks
store locks
link locks
store operation

MCQ 3: The conservative memory model that does not allow any instruction reordering on each core, is called:

sequential consistency
random consistency
remote node
host node

MCQ 4: Instruction use the same register but no flow of data between them is:

name dependency
control dependency
data dependency
none of above

MCQ 5: To update the cached copies of the data item; is the alternative protocol which is known as:

write update
write broadcast protocol
read protocol
both a and b

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