Distributed Shared Memory and Coherence MCQs with Answers PDF Download – Test 134

MCQ 666: When the calling procedure saving the registers which it wants to be preserved to access even after the call, is referred to as:

1. caller saving
2. callee saving
3. calls
4. jumps

MCQ 667: If some combination of instructions cannot be accommodated because of resource conflicts, the processor is said to have a:

1. data hazard
2. structural hazard
3. pipeline hazard
4. stall

MCQ 668: The node which has the memory location and the entry of directory of an address is:

1. home node
2. guest node
3. host node
4. all above

MCQ 669: Architecture accessing memory only with the load instruction and the store instructions, is called:

1. load-store architecture
2. load architecture
3. store architecture
4. 81x89

MCQ 670: Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operations branches and 5 cycles for memory and the relative frequencies of these operations are 40%, 20%, and 40%, respectively, then the average instruction execution time on the unpipelined processor is:

1. 4.4 ns
2. 4.2 ns
3. 3.4 ns
4. 3.2 ns