Computer Architecture MCQs – Practice Test 1 (Chapter 10)

Instruction Level Parallelism MCQs with Answers PDF Download – Test 1

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The "Instruction Level Parallelism MCQs" App Download: Having load before the store in running program order, then interchanging this order, result in a; MCQ with answers: structural hazard, waw hazard, war hazards, and control hazard. Solve Simple Implementation Scheme Quiz Questions, download Google e-Book (Free Chapter) to support study success.

Instruction Level Parallelism MCQs – Practice Test 1 PDF Download

MCQ 1: An algorithm for generating software pipelining, which is a way of increasing instruction-level parallelism by interleaving different iterations of an inner loop is known as:

global scheduling
local scheduling
pre scheduling
post scheduling

MCQ 2: Having load before the store in running program order, then interchanging this order, result in a:

waw hazard
structural hazard
war hazards
control hazard

MCQ 3: When instruction i and instruction j tend to write the same register or the memory location, it is called:

input dependence
output dependence
ideal pipeline
digital call

MCQ 4: The instruction, Add Loc,R1 in RTN is:

addsetcc loc + r1
r1<-[loc] + [r1]
r1 = loc + r1
none of above

MCQ 5: The two phases of executing an instruction are:

instruction decoding and storage
instruction execution and storage
instruction fetch and instruction execution
instruction fetch and instruction processing

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