Computer Architecture Competitive Exam MCQs – Practice Test 5 (Chapter 10)

Instruction Level Parallelism Multiple Choice Questions and Answers PDF – Test 5

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Instruction Level Parallelism MCQs with Answers PDF Download – Test 5

MCQ 21: A branch-prediction cache which is used to store the predicted address for the upcoming instruction after the branch is called a:

branch-target buffer
stations buffer
write buffer
read buffer

MCQ 22: Hardware-based speculation method for executing programs is necessarily a:

data flow speculation
control speculation
anti-speculation
all above

MCQ 23: When an instruction starts execution and when it ends execution; between these two times, the instruction is in:

execution
wait
stall
branching

MCQ 24: The operation for performing on source operands, S1 and S2 is given by the well-known field,:

MCQ 25: A hardware mechanism that aims at reducing the stall cycles resulting from correctly predicted taken branches to zero cycles are known as:

Branch Target Buffer (BTB)
Branch History Buffer (BHB)
Sequential control flow
Anti-dependence

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