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Computer Architecture Competitive Exam MCQs – Practice Test 5 (Chapter 10)

Instruction Level Parallelism MCQs with Answers PDF Download – Test 5

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Instruction Level Parallelism MCQs – Practice Test 5 PDF Download

MCQ 21: A branch-prediction cache which is used to store the predicted address for the upcoming instruction after the branch is called a:

  1. branch-target buffer
  2. stations buffer
  3. write buffer
  4. read buffer

MCQ 22: Hardware-based speculation method for executing programs is necessarily a:

  1. data flow speculation
  2. control speculation
  3. anti-speculation
  4. all above

MCQ 23: When an instruction starts execution and when it ends execution; between these two times, the instruction is in:

  1. execution
  2. wait
  3. stall
  4. branching

MCQ 24: The operation for performing on source operands, S1 and S2 is given by the well-known field,:

  1. op
  2. qj
  3. qk
  4. vj

MCQ 25: A hardware mechanism that aims at reducing the stall cycles resulting from correctly predicted taken branches to zero cycles are known as:

  1. Branch Target Buffer (BTB)
  2. Branch History Buffer (BHB)
  3. Sequential control flow
  4. Anti-dependence

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