Computer Architecture MCQs – Practice Test 8 (Chapter 13)

Memory Hierarchy Design Notes Questions with Answers PDF Download – Test 8

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Memory Hierarchy Design MCQs – Practice Test 8 PDF Download

MCQ 36: If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is a term of the Basic performance equation).:

MCQ 37: Which determines the address of I/O interface?

register select
chip select
heap
both a and b

MCQ 38: A processor for going from a user-mode to a supervisor mode, needs:

system call
kernel call
supervisor call
digital call

MCQ 39: A mapping that works well for spreading the block addresses sequentially all across the banks, are called:

sequential interleaving
spatial interleaving
sequential interaction
sequential interchange

MCQ 40: The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called:

TLB
level 2 cache
registers
level 1 cache

Memory Hierarchy Design Notes App & e-Book – Computer Architecture Admission Tests

Storage Systems MCQs

Pipelining in Computer Architecture MCQs

Interconnection Networks MCQs

Request Level and Data Level Parallelism MCQs

Instruction Set Principles MCQs

Data Level Parallelism and GPU Architecture MCQs

Exploiting Memory MCQs

Embedded Systems MCQs

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