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Computer Architecture Exam MCQs – Practice Test 4 (Chapter 13)

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Memory Hierarchy Design MCQs – Practice Test 4 PDF Download

MCQ 16: Average memory access time can be calculated as:

  1. average memory access time = hit time + miss rate * miss penalty
  2. average memory access time = hit time - miss rate * miss penalty
  3. average memory access time = hit time + miss rate _ miss penalty
  4. average memory access time = miss rate * miss penalty

MCQ 17: The circuit's dynamic nature is:

  1. SRAM
  2. DRAM
  3. TRAM
  4. DIMM

MCQ 18: An approach which does not change registers and memory's content, and it's not causing virtually memory's faults, is known as:

  1. hit penalty
  2. semantically visible
  3. semantically invisible
  4. column order

MCQ 19: Dual inline memory modules (DIMMs) typically contains:

  1. 2 to 16 DRAMs
  2. 1 to 15 DRAMs
  3. 4 to 8 DRAMs
  4. 2 to 12 DRAMs

MCQ 20: If the L2 cache is missed and the L3 cache is accessed. For a 4-core i7, which is having 8MB L3, the index size will be:

  1. 29
  2. 213
  3. 215
  4. 217

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