Computer Architecture Exam MCQs – Practice Test 4 (Chapter 13)

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Memory Hierarchy Design MCQs – Practice Test 4 PDF Download

MCQ 16: Average memory access time can be calculated as:

average memory access time = hit time + miss rate * miss penalty
average memory access time = hit time - miss rate * miss penalty
average memory access time = hit time + miss rate _ miss penalty
average memory access time = miss rate * miss penalty

MCQ 17: The circuit's dynamic nature is:

SRAM
DRAM
TRAM
DIMM

MCQ 18: An approach which does not change registers and memory's content, and it's not causing virtually memory's faults, is known as:

hit penalty
semantically visible
semantically invisible
column order

MCQ 19: Dual inline memory modules (DIMMs) typically contains:

2 to 16 DRAMs
1 to 15 DRAMs
4 to 8 DRAMs
2 to 12 DRAMs

MCQ 20: If the L2 cache is missed and the L3 cache is accessed. For a 4-core i7, which is having 8MB L3, the index size will be:

2⁹
2¹³
2¹⁵
2¹⁷

Memory Hierarchy Design Exam Prep – Computer Architecture Notes App & e-Book

Pipelining in Computer Architecture MCQs

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Computer Arithmetic MCQs

Data Level Parallelism and GPU Architecture MCQs

Exploiting Memory MCQs

Instruction Level Parallelism MCQs

Thread Level Parallelism MCQs

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