Computer Architecture MCQs – Practice Test 6 (Chapter 13)

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Memory Hierarchy Design MCQ – Practice Test 6 PDF Download

MCQ 26: Advanced cache optimization has been divided into:

2 categories
3 categories
5 categories
7 categories

MCQ 27: The instruction miss which is serviced by the main memory has total latency, approximately of:

35 processor cycles
40 processor cycles
42 processor cycles
45 processor cycles

MCQ 28: For estimating the accessing time and energy consumption of cache structure on CMOS microprocessors, the program used is:

CAD
CACTI
CACT
DAE

MCQ 29: A reliable high-end processor: the Intel Core i7 has the capability of generating two data memory references per core at every clock cycle; with 4 cores and a 3.2 GHz clock-rate, the data memory generated by i7 is:

35.6 billion 64-bit data memory/sec
25.6 billion 64-bit data memory/sec
55.6 billion 64-bit data memory/sec
22.6 billion 64-bit data memory/sec

MCQ 30: Time for replacing the block from memory, is referred to as:

hit penalty
miss penalty
hit rate
hit miss

Memory Hierarchy Design MCQ App & e-Book – Computer Architecture Entrance Exam

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