Computer Architecture MCQs – Practice Test 2 (Chapter 13)

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Memory Hierarchy Design MCQ – Practice Test 2 PDF Download

MCQ 6: The very owns way for reducing capacity misses is to increase:

hit penalty
cache hit
cache capacity
fully distributive

MCQ 7: Cache not able of containing the entire blocks needed while execution of a program, is known as:

cache full
cache hit
hit rate
cache misses

MCQ 8: When cache having size 32k, block-size 64 and set the associativity 4, will have cache index of:

(2)²
(2)⁵
(2)⁷
(2)⁹

MCQ 9: The cache with special address translation is referred to as a:

translation look aside bus
translation look aside buffer
transistor look aside buffer
transistor look aside bus

MCQ 10: Fetching the words in simple order, but as the requested block word arrives, send it towards the processor, is known as:

early restart
restarting
start before
sequential interchange

Computer Architecture Notes App & e-Book – Memory Hierarchy Design Exam Prep

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Memory Hierarchy Design MCQs

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