Digital Electronics MCQs – Practice Test 2 (Chapter 19)

Pseudo NMOS Logic Circuits MCQ with Answers PDF – Download Test 2

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Pseudo NMOS Logic Circuits MCQ PDF Download – Practice Test 2

MCQ 6: In Pseudo-NMOS circuit, when PMOS resistance is low, RC time constant will be:

high
low
zero
infinite

MCQ 7: Pseudo-NMOS inverter, NMOS will be in cutoff region when:

v_inputV_th
v_out≥ v_input -V_th
v_out≤ v_input -V_th
v_output≥V_th

MCQ 8: Four input CMOS NOR gate required:

4 transistors
5 transistors
6 transistors
8 transistors

MCQ 9: In Pseudo-NMOS logic, when the input voltage is less than threshold voltage, current drawn from supply is:

0
1
−∞
∞

MCQ 10: Pseudo-NMOS inverter, PMOS will be in saturation region when:

v_inputV_th
v_out≥ v_input -V_th
v_out≥ v_input -V_th
v_output≤V_th

Digital Electronics Notes App & e-Book – Pseudo NMOS Logic Circuits Exam Prep

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