Digital Electronics Certification MCQs – Practice Test 3 (Chapter 19)

Pseudo NMOS Logic Circuits Quiz with Answers PDF – Download Test 3

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Pseudo NMOS Logic Circuits Quiz PDF Download – Practice Test 3

MCQ 11: In Pseudo-NMOS logic, when the input voltage raise greater than threshold voltage, PMOS is in:

cutoff region
linear region
saturation region
breakdown region

MCQ 12: When the NMOS is turned ON in pseudo-NMOS logic, there exist a direct path between:

supply and output
input and output
supply and input
supply and ground

MCQ 13: When the NMOS is turned ON in pseudo-NMOS logic, static power is:

increased
decreased
infinite
doesn't change

MCQ 14: When the NMOS is turned ON in pseudo-NMOS logic, dynamic power is reduced due to:

higher capacitive loading
lower capacitive loading
lower resistive loading
higher resistive loading

MCQ 15: In Pseudo-NMOS logic, when output voltage exceeds the saturation voltage, input voltage become:

0
1
−∞
∞

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