Digital Electronics MCQs – Practice Test 9 (Chapter 7)

CMOS Logic Gates Circuits MCQs with Answers PDF – Download Test 9

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CMOS Logic Gates Circuits MCQs PDF Download – Practice Test 9

MCQ 41: In CMOS NOR gate, PDN NMOS transistors are in:

series
parallel
series or parallel
random

MCQ 42: Two networks in CMOS logic gates are operated by input variables which are:

complement of each other
equal to each other
infinite
zero

MCQ 43: PUN will conduct for all inputs combination that required:

Y(output)=0
Y(output)=1
Y(output)=-∞
Y(output)=+∞

MCQ 44: CMOS logic gate consist of:

one network
two networks
three networks
four networks

MCQ 45: In Ex-OR gate, when both inputs A and B are high, output will be:

0
1
previous state
default

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