Digital Electronics MCQs – Practice Test 2 (Chapter 7)

CMOS Logic Gates Circuits MCQ with Answers PDF Download – Test 2

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CMOS Logic Gates Circuits MCQ – Practice Test 2 PDF Download

MCQ 6: In CMOS NAND gate, PDN NMOS transistors are in:

series
parallel
series or parallel
random

MCQ 7: System in which Y is high for A input is high and simultaneously either B input is high or C and D both are high is represented as:

Y=A(B+CD)
bar(Y)=A(B+CD)
bar(Y)=A(2+CD)
bar(Y)=AB+CD

MCQ 8: PDN will conduct for all inputs combination that required:

Y(output)=0
Y(output)=1
Y(output)=-∞
Y(output)=+∞

MCQ 9: By De Morgan's Law Y=bar(A)+bar(B)bar(CD) is equals to:

bar(A)bar(B+CD)
bar(A)+bar(B)(bar(C)+D)
bar(A)+bar(B)(C+D)
bar(A)+bar(B)(bar(C)+bar(D))

MCQ 10: System in which A or B is high than output will be zero, is represented as:

Y=bar(A)+bar(B)
Y=bar(A)-bar(B)
bar(Y)=A+B
bar(Y)=bar(A+B)

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