Digital Electronics Certification MCQs – Practice Test 3 (Chapter 7)

CMOS Logic Gates Circuits Quiz with Answers PDF Download – Test 3

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Study CMOS Logic Gates Circuits Quiz App (iOS & Android) with MCQ: "When PDN and PUN are parallel, they form"; with answers: not gate, or gate, and gate, and nand gate. Study Characteristics of Standard TTL Quiz Questions, download Google Book (Free Chapter) for electronics study platforms.

CMOS Logic Gates Circuits Quiz – Practice Test 3 PDF Download

MCQ 11: When PDN and PUN are parallel, they form:

OR gate
NOT gate
AND gate
NAND gate

MCQ 12: By applying De Morgan's law to general exclusive OR gate function, we get output bar(Y)=:

AB+AB
bar(AB)+AB
A bar(B)+bar(AB)
A bar(B)+bar(A)B

MCQ 13: In NMOS circuit, current flows from:

drain to source
source to drain
gate to drain
drain to gate

MCQ 14: Transistor which act as pull-down transistor in a CMOS logic gate is:

BJT
PMOS
NMOS
BiCMOS

MCQ 15: In CMOS NOR gate, PUN PMOS transistors are in:

series
parallel
series or parallel
random

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