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Computer Architecture Study Guide: Practice Test 9 (Chapter 15)

Pipelining in Computer Architecture Multiple Choice Questions (MCQs) PDF Download - 9

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The MCQ: Indicating which of the four steps the instruction is in, is provided by; "Pipelining in Computer Architecture" App Download [Free] with answers: instruction id, instruction set, instruction decoding, and instruction status to study online school courses. Solve Shared Memory Architectures Quiz Questions, download Google eBook (Free Sample) for computer information science.

Pipelining in Computer Architecture MCQ with Answers PDF Download: Quiz 9

MCQ: 41

Indicating which of the four steps the instruction is in, is provided by

  1. instruction set
  2. instruction id
  3. instruction decoding
  4. instruction status
MCQ: 42

In pipelines with long-running operations, the possible caused issue is called

  1. in-rage completion
  2. out-of-range completion
  3. out-of-order completion
  4. in-order completion
MCQ: 43

The fetch and execution cycles are interleaved with the help of

  1. clock
  2. processor consistency
  3. link locks
  4. control unit
MCQ: 44

The effective pipeline speedup with branch penalties, assuming an ideal CPI of 1, is

  1. pipeline speedup = pipeline depth/1 + branch frequency * branch penalty
  2. pipeline speedup = pipeline depth/1 - branch frequency * branch penalty
  3. pipeline speedup = pipeline depth*(1 + branch frequency * branch penalty)
  4. pipeline speedup = pipeline depth/2 + branch frequency * branch penalty
MCQ: 45

During the execution stage, the branch and store instructions require 2 to 4 cycles and all other instructions require

  1. 2 cycles
  2. 3 cycles
  3. 4 cycles
  4. 5 cycles

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