Computer Architecture Study Guide: Practice Test 9 (Chapter 15)

Pipelining in Computer Architecture Multiple Choice Questions (MCQs) PDF Download - 9

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Pipelining in Computer Architecture MCQ with Answers PDF Download: Quiz 9

MCQ: 41

Indicating which of the four steps the instruction is in, is provided by

instruction set
instruction id
instruction decoding
instruction status

MCQ: 42

In pipelines with long-running operations, the possible caused issue is called

in-rage completion
out-of-range completion
out-of-order completion
in-order completion

MCQ: 43

The fetch and execution cycles are interleaved with the help of

clock
processor consistency
link locks
control unit

MCQ: 44

The effective pipeline speedup with branch penalties, assuming an ideal CPI of 1, is

pipeline speedup = pipeline depth/1 + branch frequency * branch penalty
pipeline speedup = pipeline depth/1 - branch frequency * branch penalty
pipeline speedup = pipeline depth*(1 + branch frequency * branch penalty)
pipeline speedup = pipeline depth/2 + branch frequency * branch penalty

MCQ: 45

During the execution stage, the branch and store instructions require 2 to 4 cycles and all other instructions require

2 cycles
3 cycles
4 cycles
5 cycles

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