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Computer Architecture Entrance Tests: Practice Test 2 (Chapter 9)
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The main memory is structured into modules each with its own address register called
The spatial locality is also known as
In terms of the no of reading accesses/program, the miss penalty in clock-cycles for reading, and the reading miss-rate, is defined as
There is a cache block of 4words, having a one-word-wide bank of DRAMs and the miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be
The range of designs between direct-mapped and fully-associative cache is called
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