Computer Architecture MCQs – Practice Test 2 (Chapter 9)

Exploiting Memory MCQ with Answers PDF Download – Test 2

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Exploiting Memory MCQ – Practice Test 2 PDF Download

MCQ 6: The main memory is structured into modules each with its own address register called:

MCQ 7: The spatial locality is also known as:

temporal locality
locality in space
locality in time
spectral locality

MCQ 8: In terms of the no of reading accesses/program, the miss penalty in clock-cycles for reading, and the reading miss-rate, is defined as:

write-stall
queue buffer
write buffer
read-stall

MCQ 9: There is a cache block of 4words, having a one-word-wide bank of DRAMs and the miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be:

0.2
0.25
0.75
1.5

MCQ 10: The range of designs between direct-mapped and fully-associative cache is called:

set definitive
set associative
fully associative
block associative

Computer Architecture Notes App & e-Book – Exploiting Memory Exam Prep

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