Computer Architecture Certification MCQs – Practice Test 3 (Chapter 5)

Computer Memory Review Quiz with Answers PDF Download – Test 3

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Computer Memory Review Quiz – Practice Test 3 PDF Download

MCQ 11: The time of CPU modeled as:

(CPU execution clock cycles + memory stall clock cycles) - clock cycle time
(CPU execution clock cycles * memory stall clock cycles) + clock cycle time
(CPU execution clock cycles + memory stall clock cycles) * clock cycle time
(CPU execution clock cycles / memory stall clock cycles) * clock cycle time

MCQ 12: The processor protection structure expand memory access protection from two levels to many, the added ones are:

rings
frames
pages
blocks

MCQ 13: The virtually indexer's limitation, saying that a direct-mapped cache can have a size no bigger than the:

page size
frame size
cache
block

MCQ 14: IA-32 allows the operating system to maintain the protection level of the:

rings
frames
pages
routine

MCQ 15: Which method is used to map logical addresses of variable length onto physical memory?

paging
overlays
segmentation
buffers

Computer Architecture Quiz App & e-Book – Computer Memory Review Certification Guide

Instruction Set Principles MCQs

Assessing Computer Performance MCQs

Storage Systems MCQs

Instruction Level Parallelism MCQs

Thread Level Parallelism MCQs

Interconnection Networks MCQs

Memory Hierarchy Design MCQs

Data Level Parallelism and GPU Architecture MCQs

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