Computer Architecture Certification MCQs – Practice Test 11 (Chapter 5)

Computer Memory Review Quiz with Answers PDF Download – Test 11

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Computer Memory Review Quiz – Practice Test 11 PDF Download

MCQ 51: If the entry is 8 bytes long, each page table has 512 entries, and the Opteron has 4 KB pages. Each of the four-level fields is 9 bits long, and the page offset is 12 bits, then the sign-extended would be:

16 bits
32 bits
64 bits
128 bits

MCQ 52: In LRU, the referenced blocks counter is set to '0' and that of the previous blocks are incremented by one and others remain same, in the case of:

hit
miss
delay time
clock

MCQ 53: The natural policy uses for the memory hierarchies: L1 data of cache are always present in L2 level of cache, refers to:

write buffer
read buffer
write-through
multilevel inclusion

MCQ 54: For reducing the chance of throwing the information which soon will be needed, this technique used is:

least recently used
random
first in, first out
first in, last out

MCQ 55: The ratio of cache accesses results in a miss is known as:

hit miss
hit rate
file caches
miss rate

Computer Architecture Quiz App & e-Book – Computer Memory Review Certification Guide

Thread Level Parallelism MCQs

Computer Arithmetic MCQs

Data Level Parallelism and GPU Architecture MCQs

Exploiting Memory MCQs

Embedded Systems MCQs

Computer Memory Review MCQs

Instruction Set Principles MCQs

Pipelining Performance MCQs

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