Bachelor Of Computer Science

Computer Architecture MCQs

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Introduction of Memory MCQ with Answers

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Introduction of Memory Multiple Choice Questions (MCQ) to solve introduction of memory quiz answers PDF worksheet, computer architecture test for online courses. Practice instruction level parallelism Multiple Choice Questions and Answers (MCQs), "Introduction of Memory" quiz questions and answers for online computer science schools. Learn mips fields, real faults and failures, designing and evaluating an i/o system, exploiting ilp using multiple issue test prep for online computer science engineering.

"The number of bits in a predictor: (m,n) is" Multiple Choice Questions (MCQ) on introduction of memory with choices 2m * 2 * number of prediction entries selected by the branch address, (2)2 * n * number of prediction entries selected by the branch address, 2m * number of prediction entries selected by the branch address, and 2m * n * number of prediction entries selected by the branch address for online computer science schools. Solve introduction of memory quiz questions for merit scholarship test and certificate programs for online college courses.

MCQs on Introduction of Memory

1.

The number of bits in a predictor: (m,n) is

2m * 2 * number of prediction entries selected by the branch address
(2)2 * n * number of prediction entries selected by the branch address
2m * number of prediction entries selected by the branch address
2m * n * number of prediction entries selected by the branch address

2.

The no of dies/wafer is approximately the area of wafer which is divided by the area of this die. It is estimated by

(? (wafer diameter/2)2\die area) + (? x wafer diameter\(2 x die area)^1\2)
(? (wafer diameter/2)2\die area)-(? x wafer diameter\(2 x die area)^1\2)
(? (wafer diameter/2)2\die area)*(? x wafer diameter\(2 x die area)^1\2)
(? (wafer diameter/2)2\die area)\(? x wafer diameter\(2 x die area)^1\2)

3.

When the processor gets the requested data items from the cache is known as

file caches
name cache
cache hit
registers

4.

Adding the 0.1 ms ATA controller overhead means 0.2 ms to 0.5 ms per I/O, making the maximum rate per controller

500 IOPS and 300 IOPS
5000 IOPS and 3000 IOPS
3000 IOPS and 2000 IOPS
5000 IOPS and 2000 IOPS

5.

The virtual memory stores the next segment of data to be executed on the

cache
ram
secondary storage
rom

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