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Digital Logic Design Practice Test 23

# Design Procedure in Combinational Logics Quiz PDF: Questions and Answers - 23

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The Quiz: Half subtractor is used to perform subtraction of; "Design Procedure in Combinational Logics" App (iOS & Android) with answers: 3 bits; 2 bits; 4 bits; 5 bits; for associates in computer science. Study Combinational Logics Questions and Answers, Google eBook to download free sample for online degrees.

## Design Procedure in Combinational Logics Questions and Answers : Quiz 23

MCQ 111:

Half subtractor is used to perform subtraction of

1. 2 bits
2. 3 bits
3. 4 bits
4. 5 bits
MCQ 112:

The negative logic is symbolized with

1. 1
2. 0
3. up
4. down
MCQ 113:

Delay is measured with the unit

1. nW
2. ns
3. mW
4. mm
MCQ 114:

A register that is capable of shifting its binary information either to the left or the Right side is called as

1. Latch register
2. flip-flops
3. binary register
4. Shift Register
MCQ 115:

2k adjacent squares in an N variable map will have literals having a value of

1. k
2. N
3. k-N
4. N-k

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