Digital Logic Design Online Tests
State Reduction and Assignment MCQ (Multiple Choice Questions) PDF Download
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State Reduction and Assignment MCQs: Questions and Answers PDF Download
The reduction of flip-flops in a sequential circuit is referred to as
- reduction
- state reduction
- next state
- mid state
Unused states are treated as Don't cares conditions during the
- Design of a circuit
- Execution
- Pulse trigger
- edge trigger
When both inputs of a J-K flip-flop cycle, the output will be
- invalid
- change
- not change
- toggle
Two states are said to be equal if they have the same
- inputs
- next state
- output
- mid state
Which one of the following is an example of the use of an S-R flip-flop?
- transition pulse generator
- racer
- switch debouncer
- astable oscillator
Digital Logic Design Practice Tests
State Reduction and Assignment Textbook App: Free Download (Android & iOS)
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