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MCQ 211: The procedure to save registers in stack segments is known as

  1. activation record
  2. procedure frame
  3. queue
  4. both a and b

MCQ 212: There is a cache block of 4words, having a one-word-wide bank of DRAMs and the miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be

  1. 0.2
  2. 0.25
  3. 0.75
  4. 1.5

MCQ 213: The cache with special address translation is referred to as a

  1. translation look aside bus
  2. translation look aside buffer
  3. transistor look aside buffer
  4. transistor look aside bus

MCQ 214: MIPS architecture provides a separate pair of 32-bit registers to contain the product of 64-bits called

  1. Hi
  2. Lo
  3. To
  4. both a and b

MCQ 215: The assembly language instruction corresponding to the machine code 00af8020hex is

  1. sub $s0,$a1,$t7
  2. add $s0,$a1,$t7
  3. mul $s0,$a1,$t7
  4. addi $s0,$a1,$t7

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