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Computer Architecture Competitive Exam MCQs – Practice Test 5 (Chapter 15)

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Pipelining in Computer Architecture MCQs – Practice Test 5 PDF Download

MCQ 21: Pipelining increases the CPU instruction:

  1. size
  2. through put
  3. cycle rate
  4. time

MCQ 22: Control hazards can cause a greater performance loss for MIPS pipeline than do:

  1. stall
  2. data hazard
  3. structural hazard
  4. branch hazard

MCQ 23: If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have:

  1. exception handling
  2. imprecise exceptions
  3. error correction
  4. none of above

MCQ 24: The presence of anti-dependence and output dependencies leads to:

  1. war and waw stalls
  2. war stall
  3. waw stall
  4. win stall

MCQ 25: The process of letting an instruction move from decode stage into the execution stage of this pipeline is usually called:

  1. canceling
  2. instruction issue
  3. nullifying
  4. branch prediction

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