Computer Architecture Competitive Exam MCQs – Practice Test 5 (Chapter 15)

Pipelining in Computer Architecture MCQs with Answers PDF Download – Test 5

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Pipelining in Computer Architecture MCQs – Practice Test 5 PDF Download

MCQ 21: Pipelining increases the CPU instruction:

size
through put
cycle rate
time

MCQ 22: Control hazards can cause a greater performance loss for MIPS pipeline than do:

stall
data hazard
structural hazard
branch hazard

MCQ 23: If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have:

exception handling
imprecise exceptions
error correction
none of above

MCQ 24: The presence of anti-dependence and output dependencies leads to:

war and waw stalls
war stall
waw stall
win stall

MCQ 25: The process of letting an instruction move from decode stage into the execution stage of this pipeline is usually called:

canceling
instruction issue
nullifying
branch prediction

Pipelining in Computer Architecture MCQs App & e-Book – Computer Architecture Competitive Exam

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