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Computer Architecture Prep Tests

Computer Architecture Tests

Distributed Shared Memory and Coherence MCQ with Answers PDF Download

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Computer Architecture: Distributed Shared Memory and Coherence MCQs PDF Download

MCQ: When performing a looping operation, the instruction gets stored in the

A) memory
B) cache
C) registers
D) system heap

MCQ: Splitting the cache into separate instruction and data caches or by using a set of buffers, usually called

A) cache buffer
B) data buffer
C) instruction buffer
D) none of above

MCQ: The median vectorization getting improved from about 70% to about

A) 0.75
B) 0.8
C) 0.9
D) 1

MCQ: Control hazards can cause a greater performance loss for MIPS pipeline than do

A) stall
B) data hazard
C) structural hazard
D) branch hazard

MCQ: Storing the arrays as row by row order is referred to as

A) row major order
B) column major order
C) row order
D) column order

Practice Tests: Computer Architecture Exam Prep

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