Computer Architecture MCQs – Practice Test 2 (Chapter 16)

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The "Pipelining Performance MCQ" App Download (Android & iOS): Instruction being read from memory using the address placed in the PC and then it is placed in the IF/ID pipeline register in; MCQ with answers: instruction decode stage, instruction fetch stage, execution, and memory access. Practice Introduction of Memory Quiz Questions, download Apple Book (Free Chapter) to achieve computer mastery.

Pipelining Performance MCQ – Practice Test 2 PDF Download

MCQ 6: Pipeline stalling is also known as:

load-use
data hazards
bubble
multicycle data path

MCQ 7: The instruction being read from memory using the address placed in the PC and then it is placed in the IF/ID pipeline register in:

instruction fetch stage
instruction decode stage
execution
memory access

MCQ 8: Predicting the branches by using runtime information at runtime is known as:

static branch prediction
dynamic branch prediction
branch prediction
stall prediction

MCQ 9: To discard instructions in the pipeline is referred to as:

load-use
flushing
decoding
discarding

MCQ 10: Delay in finding the proper instruction to fetch is known as control hazard, also referred to as:

structural hazards
data hazards
branch hazard
call hazard

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