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Computer Architecture MCQs – Practice Test 7 (Chapter 7)

Data Level Parallelism and GPU Architecture Quiz with Answers PDF Download – Test 7

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Data Level Parallelism and GPU Architecture Quiz – Practice Test 7 PDF Download

MCQ 31: Pipeline having stalls are required only a single time per vector instruction, instead of once per:

  1. vector register
  2. vector element
  3. chaining
  4. line prediction

MCQ 32: The memory bandwidth of the GPU is:

  1. 4.4* the memory bandwidth
  2. 2.4* the memory bandwidth
  3. 3.4* the memory bandwidth
  4. 5.4* the memory bandwidth

MCQ 33: The two iteration indices, j and k, and these both are in the limits of the FOR loop, for-loop index variable which runs from m to n i.e.:

  1. m ≤ j ≤ n, m ≤ k ≤ n
  2. m ≥ a ≥ n, m ≥ k ≥ n
  3. m < j < n, m < b < n
  4. m > j > 2, m > k > 3

MCQ 34: The time lost due to the branch instruction is often referred to as:

  1. latency
  2. delay
  3. branch penalty
  4. none of above

MCQ 35: The PTx instruction having the format: opcode. type d, a, b, c; where d is the:

  1. destination
  2. domain
  3. data
  4. double

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