Computer Architecture Competitive Exam MCQs – Practice Test 5 (Chapter 5)

Computer Memory Review MCQs with Answers PDF Download – Test 5

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Computer Memory Review MCQs – Practice Test 5 PDF Download

MCQ 21: If the processor is not willing in the cycle for retiring the maximum number of instructions; it is said to be:

in a stalled clock cycle
write-back
write-through
read through

MCQ 22: The security loopholes prevent by not allowing the user process to ask the operating system to access something indirectly are known as:

Blocks
Frames
Trojan horses
Routines

MCQ 23: When the processor is waiting for write instruction to complete during the write-through process, the processor is said to:

read back
write-back
read stall
write stall

MCQ 24: If a set has n blocks, the cache placement is then called:

2-way set distributive
2-way set associative
n-way setting
n-way set associative

MCQ 25: For reducing the frequency on replacement of write-back blocks, the commonly used feature, is known as:

hit miss
index field
write-through
dirty bit

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