Digital Logic Design MCQs – Practice Test 10 (Chapter 12)

Synchronous Sequential Logics MCQ with Answers PDF Download – Test 10

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Synchronous Sequential Logics MCQ – Practice Test 10 PDF Download

MCQ 46: Flip-flops are sensitive to:

feedback path
pulses
signals
pulse transition

MCQ 47: A flip-flop circuit can be constructed by two NAND gates or:

with Two AND gates
with Two OR Gates
with Two NOR gates
with two NOT gates

MCQ 48: Latches developed with NOR and NAND gate tend to stay in the latched condition because of which configuration feature?

low input voltages
synchronous operation
gate impedance
cross coupling

MCQ 49: The truth table for an S-R flip-flop has how many VALID entries?

MCQ 50: The state diagram provides the same information as the:

flip-flops provides
State table provides
truth table provides
latches

Digital Logic Design Notes App & e-Book – Synchronous Sequential Logics Exam Prep

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