Computer Architecture Practice Test 112

Pipelining Crosscutting Issues Multiple Choice Questions (MCQ) PDF - 112

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Pipelining Crosscutting Issues Questions and Answers PDF Download: Quiz 112

MCQ 556: Two-way set associative having a 64-byte block, the single clock-cycle hit time is a

A) level 1 instruction cache

B) level 1 data cache

C) level 2 data cache

D) level 2 instruction cache

MCQ 557: The internal components of the processor are connected by

A) processor intra-connectivity circuitry

B) processor bus

C) memory bus

D) rambus

MCQ 558: Indicating which of the four steps the instruction is in, is provided by

A) instruction set

B) instruction id

C) instruction decoding

D) instruction status

MCQ 559: To provide for protected sharing, half of the address space is shared by all processes and half is unique to each process is called

A) global address space

B) local address space

C) address bit

D) both a and b

MCQ 560: Breaking the instruction's execution into clock cycles are divided into

A) two steps

B) three steps

C) four steps

D) five steps

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