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Computer Architecture Practice Test 112

Pipelining Crosscutting Issues Quiz Questions PDF Download - 112

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MCQ: Two-way set associative having a 64-byte block, the single clock-cycle hit time is a

A) level 1 instruction cache
B) level 1 data cache
C) level 2 data cache
D) level 2 instruction cache

MCQ: The internal components of the processor are connected by

A) processor intra-connectivity circuitry
B) processor bus
C) memory bus
D) rambus

MCQ: Indicating which of the four steps the instruction is in, is provided by

A) instruction set
B) instruction id
C) instruction decoding
D) instruction status

MCQ: To provide for protected sharing, half of the address space is shared by all processes and half is unique to each process is called

A) global address space
B) local address space
C) address bit
D) both a and b

MCQ: Breaking the instruction's execution into clock cycles are divided into

A) two steps
B) three steps
C) four steps
D) five steps

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