Computer Architecture MCQs – Practice Test for Exam Prep

Thread Level Parallelism Multiple Choice Questions with Answers – PDF Download

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Thread Level Parallelism MCQs PDF Download – Prep Test

MCQ 1: A bus which is designed for allowing processors, I/O devices and memory, is called a:

processor-memory bus
bus transaction
synchronous bus
backplane bus

MCQ 2: The on-chip memory which is local to every multithreaded Single Instruction Multiple Data (SIMD) Processor is called:

local memory
global memory
flash memory
stack

MCQ 3: For reducing the frequency on replacement of write-back blocks, the commonly used feature, is known as:

hit miss
index field
write-through
dirty bit

MCQ 4: The circuit's dynamic nature is:

SRAM
DRAM
TRAM
DIMM

MCQ 5: Equivalent to the PTE valid bit used to indicate the valid translation is referred to as:

base field
present bit
access bit
attributes field

Computer Architecture MCQs App & e-Book – Thread Level Parallelism Practice Tests

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