Computer Architecture Practice Test 46

Introduction to Pipelining MCQ Questions PDF - 46

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Computer Architecture: Introduction to Pipelining MCQ Quiz PDF Download

MCQ: Many network interface cards implement hardware timers as well as hardware support to split messages into packets and reassemble them, compute the

A) cyclic redundancy check

B) acyclic redundancy check

C) cyclic redundancy checksum

D) acyclic redundancy checksum

MCQ: A common optimization for reducing write stalls is a

A) write buffer

B) write-back

C) read stall

D) write stall

MCQ: If a unit completes its task before the allotted time period, then

A) it'll perform some other task in the remaining time

B) its time gets reallocated to a different task

C) it'll remain idle for the remaining time

D) none of above

MCQ: The index of the instruction cache is

A) 2index = cache size- block size * set associativity

B) 2index = cache size/ block size + set associativity

C) 2index = cache size + block size * set associativity

D) 2index = cache size/ block size * set associativity

MCQ: Pipelining increases the CPU instruction

A) size

B) through put

C) cycle rate

D) time

Mock Tests: Computer Architecture Course Prep

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