Introduction to Pipelining MCQ (Multiple Choice Questions) PDF - 46

MCQ 226: Many network interface cards implement hardware timers as well as hardware support to split messages into packets and reassemble them, compute the

1. cyclic redundancy check
2. acyclic redundancy check
3. cyclic redundancy checksum
4. acyclic redundancy checksum

MCQ 227: A common optimization for reducing write stalls is a

1. write buffer
2. write-back
3. read stall
4. write stall

MCQ 228: If a unit completes its task before the allotted time period, then

1. it'll perform some other task in the remaining time
2. its time gets reallocated to a different task
3. it'll remain idle for the remaining time
4. none of above

MCQ 229: The index of the instruction cache is

1. 2index = cache size- block size * set associativity
2. 2index = cache size/ block size + set associativity
3. 2index = cache size + block size * set associativity
4. 2index = cache size/ block size * set associativity

MCQ 230: Pipelining increases the CPU instruction

1. size
2. through put
3. cycle rate
4. time