Digital Logic Design MCQs – Practice Test 6 (Chapter 8)

MSI and PLD Components MCQ with Answers PDF Download – Test 6

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MSI & PLD Components MCQ – Practice Test 6 PDF Download

MCQ 26: MSI stands for:

Small Scale Integration
Medium Scale Integration
Mask Scale Integration
Median Scale Integration

MCQ 27: The limiting factor on a speed of parallel adder is:

input delay
carry propagation delay
input propagation delay
output delay

MCQ 28: A multiplexer is also known as a:

Coder
parallel adder
Data selector
NOR gate

MCQ 29: Binary Coded Decimal (BCD) adder can be constructed with 3 Integrated Circuits (IC) packages each of:

2bits
3bits
4bits
5bits

MCQ 30: The two input multiplexer would have:

1 select line
2 select lines
4 select lines
3 select lines

MSI & PLD Components MCQ App & e-Book – Digital Logic Design Entrance Exam

Registers Counters and Memory Units MCQs

DLD Lab Equipment and Experiments MCQs

Binary Systems MCQs

Simplification of Boolean Functions MCQs

Standard Graphic Symbols MCQs

Asynchronous Sequential Logic MCQs

Algorithmic State Machine MCQs

MSI and PLD Components MCQs

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