Digital Logic Design Certification MCQs – Practice Test 11 (Chapter 7)

DLD Lab Equipment and Experiments Quiz with Answers PDF Download – Test 11

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DLD Lab Equipment & Experiments Quiz – Practice Test 11 PDF Download

MCQ 51: Number of gates for the full adder can be reduced if JK flip-flop is used for:

storing the carry
subtracting the carry
adding the carry
deleting the carry

MCQ 52: Input clock of RS flip-flop is given to:

input
pulsar
output
master slave flip-flop

MCQ 53: 74195 shifter register has:

parallel load
serial load
parallel store
serial store

MCQ 54: Read Only Memory (ROM) simulator is obtained from Random Access Memory (RAM) when it is operated in the:

read only mode
write only mode
read and write mode
write only mode

MCQ 55: A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The least yield frequency conceivable is?

4input NAND
3input NAND
5input NAND
6input NAND

Digital Logic Design Quiz App & e-Book – DLD Lab Equipment & Experiments Certification Guide

DLD Lab Equipment and Experiments MCQs

Digital Integrated Circuits MCQs

Binary Systems MCQs

Standard Graphic Symbols MCQs

Asynchronous Sequential Logic MCQs

Algorithmic State Machine MCQs

Boolean Algebra and Logic Gates MCQs

Registers Counters and Memory Units MCQs

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