Digital Electronics MCQs - Chapter 19
Pseudo NMOS Logic Circuits Trivia Questions and Answers PDF - 8
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Pseudo NMOS Logic Circuits Questions & Answers PDF Download: MCQ Quiz 8
MCQ 36: In Pseudo-NMOS circuit, PMOS pull-up gate is
- input signal
- output signal
- supply
- grounded
MCQ 37: Saturation voltage is equals to
- VDD+Vth
- VDD-Vth
- Vth
- VDDxVth
MCQ 38: Pseudo-NMOS is particularly suitable for application s in which output
- switch fast
- switch slow
- remains low
- remains high
MCQ 39: Enhancement MOSFETs were replaced by depletion MOSFETs to utilize it as load in mid
- 1951s
- 1961s
- 1971s
- 1981s
MCQ 40: Four input Pseudo-NMOS NOR gate required
- 4 transistors
- 5 transistors
- 6 transistors
- 8 transistors
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Pseudo NMOS Logic Circuits MCQ Book Questions
- When electrons reaches the drain end of channel, they acquire
- Bits that are to be ignored in digital masking are called
- In DCFL, depletion MESFET is used for
- A class of electronic circuits that reduce the storage time of a
- Arbiter electronics is an example of
- In SPICE, non linear quiescent point calculation is termed as