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Instruction Level Parallelism Multiple Choice Questions and Answers PDF p. 1

Practice Instruction Level Parallelism multiple choice questions and answers, CS quiz answers PDF to solve Computer Architecture worksheets 1 for online colleges. Solve exploiting ilp using multiple issue MCQs, Instruction Level Parallelism trivia questions and answers for admission and merit scholarships test. "Instruction Level Parallelism MCQ" PDF book: exploiting ilp using multiple issue, designing and evaluating an i/o system, real faults and failures, mips fields, signed and unsigned numbers career test to learn free online courses.

"An algorithm for generating software pipelining, which is a way of increasing instruction-level parallelism by interleaving different iterations of an inner loop is known as" Multiple Choice Questions (MCQ) on instruction level parallelism with choices local scheduling, global scheduling, pre scheduling, and post scheduling for information and communication technology. Practice exploiting ilp using multiple issue quiz questions for jobs' assessment test and online courses for top computer science schools in the world.

MCQs on Instruction Level Parallelism Quiz

1.

An algorithm for generating software pipelining, which is a way of increasing instruction-level parallelism by interleaving different iterations of an inner loop is known as

global scheduling
local scheduling
pre scheduling
post scheduling

2.

Having load before the store in running program order, then interchanging this order, result in a

waw hazard
structural hazard
war hazards
control hazard

3.

When instruction i and instruction j tend to write the same register or the memory location, it is called

input dependence
output dependence
ideal pipeline
digital call

4.

The instruction, Add Loc,R1 in RTN is

addsetcc loc + r1
r1<-[loc] + [r1]
r1 = loc + r1
none of above

5.

The two phases of executing an instruction are

instruction decoding and storage
instruction execution and storage
instruction fetch and instruction execution
instruction fetch and instruction processing