Engineering Courses

Chapter 9: Digital Electronics Exam Tests

Digital Electronics MCQs - Chapter 9

Dynamic Logic Circuits Multiple Choice Questions PDF Download - 5

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Dynamic Logic Circuits Questions & Answers PDF Download: MCQ Quiz 5

MCQ 21: Cascading is not easily possible in

A) TTL logic
B) PTL logic
C) CMOS logic
D) Dynamic Logic

MCQ 22: In Dynamic logic when clock signal is low, PMOS turned ON and this phase is termed as

A) precharge phase
B) charge phase
C) discharge phase
D) evaluation phase

MCQ 23: As output of DOMINO CMOS gate is low, premature capacitance will

A) charge
B) discharge
C) doesn't change
D) remains constant

MCQ 24: For every 10° rise of temperature, current

A) increase double
B) increase triple
C) decrease double
D) decrease triple

MCQ 25: In Dynamic logic when clock signal is high, PMOS turned OFF and this phase is termed as

A) precharge phase
B) charge phase
C) discharge phase
D) evaluation phase

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Dynamic Logic Circuits App (Android & iOS)

Dynamic Logic Circuits App (Android & iOS)

Digital Electronics App (Android & iOS)

Digital Electronics App (Android & iOS)

Engineering Math App (Android & iOS)

Engineering Math App (Android & iOS)

Electronic Devices App (Android & iOS)

Electronic Devices App (Android & iOS)