Computer Architecture MCQs - Chapter 27

Pipelining Performance Quiz Questions and Answers PDF - 3

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Pipelining Performance Questions & Answers PDF Download: MCQ Quiz 3

MCQ 11: Make a decision based on the results of the above instruction while it's being executed, is referred to as

structural hazards
data hazards
control hazard
pipelining

MCQ 12: Branch, MemWrite, and MemRead are control lines set of

instruction fetch
instruction decode
memory access
execution

MCQ 13: The given set of instructions add $s0, $t0, $t1; sub $t2, $s0, $t3; shows the

structural hazards
data hazards
forwarding bypassing
pipeline stall

MCQ 14: In instruction execution of the pipelined processor, the WB stage is the

first stage
third stage
forth stage
fifth stage

MCQ 15: In pipelined instruction time between instructions, assuming ideal conditions, is equal to

time between instructions pipelined = time between instruction\ no of piped stages
time between instructions pipelined = no of piped stages
time between instructions pipelined = time between instruction
none

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