Computer Architecture MCQs - Chapter 23

Memory Hierarchy Design MCQ (Multiple Choice Questions) PDF - 6

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Memory Hierarchy Design Questions & Answers PDF Download: MCQ Quiz 6

MCQ 26: Advanced cache optimization has been divided into

A) 2 categories

B) 3 categories

C) 5 categories

D) 7 categories

MCQ 27: The instruction miss which is serviced by the main memory has total latency, approximately of

A) 35 processor cycles

B) 40 processor cycles

C) 42 processor cycles

D) 45 processor cycles

MCQ 28: For estimating the accessing time and energy consumption of cache structure on CMOS microprocessors, the program used is

A) CAD

B) CACTI

C) CACT

D) DAE

MCQ 29: A reliable high-end processor: the Intel Core i7 has the capability of generating two data memory references per core at every clock cycle; with 4 cores and a 3.2 GHz clock-rate, the data memory generated by i7 is

A) 35.6 billion 64-bit data memory/sec

B) 25.6 billion 64-bit data memory/sec

C) 55.6 billion 64-bit data memory/sec

D) 22.6 billion 64-bit data memory/sec

MCQ 30: Time for replacing the block from memory, is referred to as

A) hit penalty

B) miss penalty

C) hit rate

D) hit miss

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