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Chapter 23: Computer Architecture Exam Tests

Computer Architecture MCQs - Chapter 23

Memory Hierarchy Design MCQ (Multiple Choice Questions) PDF - 2

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Memory Hierarchy Design Questions & Answers PDF Download: MCQ Quiz 2

MCQ 6: The very owns way for reducing capacity misses is to increase

A) hit penalty
B) cache hit
C) cache capacity
D) fully distributive

MCQ 7: Cache not able of containing the entire blocks needed while execution of a program, is known as

A) cache full
B) cache hit
C) hit rate
D) cache misses

MCQ 8: When cache having size 32k, block-size 64 and set the associativity 4, will have cache index of

A) (2)2
B) (2)5
C) (2)7
D) (2)9

MCQ 9: The cache with special address translation is referred to as a

A) translation look aside bus
B) translation look aside buffer
C) transistor look aside buffer
D) transistor look aside bus

MCQ 10: Fetching the words in simple order, but as the requested block word arrives, send it towards the processor, is known as

A) early restart
B) restarting
C) start before
D) sequential interchange

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Memory Hierarchy Design App (Android & iOS)

Memory Hierarchy Design App (Android & iOS)

Computer Architecture App (Android & iOS)

Computer Architecture App (Android & iOS)

Computer Networks App (Android & iOS)

Computer Networks App (Android & iOS)

Computer Basics App (Android & iOS)

Computer Basics App (Android & iOS)