Computer Architecture MCQs - Chapter 17

Instruction Level Parallelism Multiple Choice Questions (MCQ) PDF - 8

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Instruction Level Parallelism Questions & Answers PDF Download: MCQ Quiz 8

MCQ 36: An increasing scheme for the number of instructions, relative to the overhead and branch instructions is

loop rolling
loop unrolling
looping
unrooling

MCQ 37: Allowing multiple instructions for issuing in a clock cycle, is the goal of

single-issue processors
dual-issue processors
multiple-issue processors
no-issue processors

MCQ 38: For predicting the value which will be produced by instruction, this stated technique is referred to as

value prediction
anti-dependence
anti-speculation
commit

MCQ 39: Attempts for predicting the result of a computation used technique is called

data prediction
flow prediction
value prediction
line prediction

MCQ 40: In the scheme, named as Tomasulo's scheme, register renaming is done by

preservatives
tournament predictors
reservation stations
registers

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